Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1032 IP
251
1.0
SMIC 0.18um LL IO Library
SMIC 0.18um LL process 1.8v/3.3v Generic IO library...
252
1.0
SMIC 0.18um LVDS Transceiver
The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial stream. This single s...
253
1.0
SMIC 0.18um LVDS Transceiver/Receiver
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between of them can be up to 700Mhz. The L...
254
1.0
SMIC 0.18um Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 48-bit or 36-bit RGB parallel data into 6-pair/3-pair of Mini-LVDS data stream that can support transmission ...
255
1.0
SMIC 0.18um SSTL2
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
256
1.0
SMIC 0.18um SSTL3
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
257
1.0
SMIC 0.18um SSTL_18 I/O
SSTL_18 (Stub Series Terminated Logic for 1.8v) is an electrical interface commonly used with DDR2....
258
1.0
SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
259
1.0
SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
260
1.0
SMIC 55nm LP Multiple Power Supply IO library
Multiple power supply IO library for SMIC55nm low power 1.2v/2.5v process...
261
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
262
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
263
1.0
SMIC 65nm Low Leakage LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core that can support Sin...
264
1.0
SMIC13 High Speed process, 1.2/1.5V High Speed Transceiver Logic IO
VeriSilicon SMIC 0.13um 1.2V/1.5V HSTL I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...
265
1.0
SMIC18 General process, Multi-Voltage IO with high voltage voltence
SMIC18 General process, Multi-Voltage IO, driver current: 2mA~16mA when 3.3v IO supply...
266
1.0
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA...
267
1.0
SMIC18 General process, Multi-Voltage IO, High ESD perfermance
SMIC18 General process, Multi-Voltage IO, High ESD perfermance...
268
1.0
DN110: Multi-Voltage 1.2-3.3V fail-safe GPIO/ODIO with analog mux, Dongbu HiTek 110nm
A silicon-proven wirebond I/O library in Dongbu HiTek 110nm (11SB) with a multi-voltage, multi-standard fail-safe GPIO and I2C-targeted open-drain cap...
269
1.0
DN130: 5V Fail-Safe GPIO, GPI, & I2C ODIO Library, Dongbu HiTek 130nm
A flip-chip-compatible I/O library in Dongbu HiTek 130nm with a 5V fail-safe GPIO, two standard 5V GPIOs (regular and reduced-footprint), a 5V general...
270
1.0
Sony Camera LVDS Interface
The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA. It serves as a direct replacement for an exte...
271
1.0
RP65: Multi-Voltage GPIO with PWM, I2C/SVID open-drain, 3.3V/5V analog & OTP, TSMC 65nm
A silicon-proven, wirebond I/O library in TSMC 65nm with dual independent I/O supply rails (1.0–3.3V and 3.3V) and power-on control (POC) to hold I/Os...
272
1.0
Programmable Special IO in SMIC0.13um
AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/18. The IP is extreme...
273
1.0
MS18: 1.2-1.8V GPIO with 1.8V/5V analog/RF, 20-36V HV analog & OTP cell, TSMC 180nm
A silicon-proven Certus I/O library for TSMC 180nm, built to fill gaps in the native foundry I/O offering at this node. It pairs a 1.2–1.8V GPIO (dual...
274
1.0
RS18: 1.8V GPIO with 1.8V/3.3V analog I/O, TSMC 180nm BCD
Certus' silicon-proven I/O library in TSMC 180nm BCD, built for mixed-signal, power-management, and BCD applications. It combines a 1.8V digital I/O (...
275
1.0
HS18: 1.8V to 5V GPIO & analog I/O library, TSMC 180nm BCD
A silicon-proven, flip-chip-compatible I/O library in TSMC 180nm BCD. It pairs multi-voltage GPIO and 1.8V–5V analog I/O with ultra-low-capacitance, l...
276
1.0
MS55: Multi-voltage analog I/O Library with custom 12V ESD, GlobalFoundries 55nm BCD Lite
A silicon-proven, flip-chip-optimized analog and mixed-signal I/O library in GlobalFoundries 55nm BCD Lite, providing 1.8V, 3.3V, 5V, and 12V analog I...
277
1.0
IS55: Specialized 20V Analog ESD Cell, TSMC 55nm LP
A silicon-proven 20V ESD protection cell in TSMC 55nm LP, built for high-voltage interfaces in analog, mixed-signal, RF, and power-management ICs. Its...
278
1.0
NSI 0.13um RFSOI Process Multiple power supply IO library
NSI 0.13um RFSOI 1.8V/2.5V Multiple power supply IO Library...
279
1.0
GSMC 0.11um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between them can be up to 650Mhz. The LVDS...
280
1.0
GSMC 0.13um IO Library
GSMC 0.13um process 1.2v/3.3v Generic IO library...
281
1.0
CSMC 0.13um IO Library
CSMC 0.13um process 1.2v/3.3v Generic IO library...
282
1.0
GSMC 0.13um LP IO Library
GSMC 0.13um LP process 1.2v/3.3v Generic IO library...
283
1.0
CSMC 0.13um LP IO Library
CSMC 0.13um LP process 1.2v/3.3v Generic IO library...
284
1.0
TSMC 0.13um LVDS Transmitter
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...
285
1.0
GSMC 0.14um LV IO Library
GSMC 0.14um LV process 1.2v/3.3v Generic IO library...
286
1.0
GSMC 0.15um IO Library
GSMC 0.15um process 1.5v/3.3v Generic IO library...
287
1.0
GSMC 0.15um LP IO Library
GSMC 0.15um LP process 1.5v/3.3v Generic IO library...
288
1.0
GSMC 0.15um LV IO Library
GSMC 0.15um LV process 1.5v/3.3v Generic IO library...
289
1.0
GSMC 0.15um ULP IO Library
GSMC 0.15um ULP process 1.8v/2.8v Generic IO library...
290
1.0
GSMC 0.16um IO Library
GSMC 0.16um process 1.8v/3.3v Generic IO library...
291
1.0
CSMC 0.16um IO Library
CSMC 0.16um process 1.8v/3.3v Generic IO library...
292
1.0
GSMC 0.18um 1.8V/3.3V DUP I/O Library
VeriSilicon GSMC 0.18um 1.8V/3.3V DUP I/O Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18u...
293
1.0
GSMC 0.18um 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (02) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing (GSMC) 0....
294
1.0
GSMC 0.18um 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (03) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporati...
295
1.0
GSMC 0.18um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between them can be up to 650Mhz. The LVDS...
296
1.0
GSMC 0.18um cost effective IO Library
GSMC 0.18um G9 process 3.3v/3.3v Generic IO library...
297
1.0
GSMC 0.18um cost effective IO Library
GSMC 0.18um G9 process 3.3v/5v Generic IO library...
298
1.0
GSMC 0.18um Crystal Oscillator IO
This is a crystal oscillator IO pad designed for low-power consumption application. The OSC power supply is 3.3V, and the IO pad provides clock signal...
299
1.0
GSMC 0.18um IO Library
GSMC 0.18um process 1.8v/3.3v Generic IO library...
300
1.0
CSMC 0.18um IO Library
CSMC 0.18um process 1.8v/3.3v Generic IO library...